1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, in particular, to a nonvolatile semiconductor memory device capable of storing multiple bits in one memory cell, and to a method of operating the same.
2. Description of the Related Art
NAND flash memory is known as one of nonvolatile semiconductor memory devices. This NAND flash memory has a memory cell array including a plurality of NAND cell units. Each NAND cell unit is configured by a plurality of memory cells connected in series and two select transistors connected to both ends thereof.
Each memory cell stores, in an erase state, data “1” having a negative threshold voltage. In a data write operation, electrons are injected into a floating gate to write data “0” having a positive threshold voltage. The NAND flash memory may change the threshold voltage only from a lower value to a higher value in a data write operation, and may change the threshold voltage in the reverse direction (from a higher value to a lower value) only by an erase operation on a block basis.
To increase memory capacity, current technology has developed so-called multi-value NAND flash memory to store two or more bits of information in one memory cell. For example, when 2 bits are stored in one memory cell, one memory cell has 22=4 different threshold voltage distributions. A write operation in the case of storing 4 values (2 bits) of information in one memory cell in the NAND flash memory is performed as follows. First, subsequent to applying a write voltage Vpgm having an initial value Vpgmi (for example, about 15 V) to a control gate of the memory cell subject to the write operation, a verify judgment is performed. If, as a result of the verify judgment, the write operation is judged to be incomplete, the write voltage Vpgm is stepped up in increments of 0.1 V-1 V, and the write operation is re-performed using this stepped-up write voltage Vpgm. By repeating the verify judgment and the write operation at the stepped up write voltage in such a way, the write operation is performed sequentially from a low threshold voltage distribution (Japanese Unexamined Patent Application Publication No. 2007-004861).
This kind of multi-value storage NAND flash memory has the problem that the number of applications (number of step-ups) of the write voltage Vpgm applied to the control gate of the memory cell differs according to the data to be stored, resulting in a lengthening of write time. Consider, for example, the case of attempting to assign four different threshold voltage distributions Er, A, B, and C (Er<A<B<C) to one memory cell. In this case, if the applied voltage is the same, the number of applications of the write voltage Vpgm required to change from distribution Er to distribution C is greater than that required to change from distribution Er to distribution A. Consequently, in the case that each of the threshold voltage distributions Er, A, B, and C are assigned to a plurality of memory cells along a single word line, the write operation for memory cells where distribution A is to be written is completed in a small number of applications, while the write operation for memory cells where distribution C is to be written requires a greater number of applications. If, to reduce the number of applications, the initial value Vpgmi of the write voltage Vpgm is increased or a step-up width is increased, there is a risk that an erroneous write occurs in the memory cells where the low threshold voltage distribution A is to be written. The initial value and step-up width must therefore beset in line with the case where data of the low threshold voltage distribution is written, and this results in a lengthening of the write time.